14 search results - page 2 / 3 » A Multi-Band Burst-Mode Clock and Data Recovery Circuit |
123
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ISCAS
2008
IEEE
16 years 11 days ago
2008
IEEE
— This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass tran...
146
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CCECE
2009
IEEE
15 years 10 months ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
167
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
188
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TVLSI
2010
15 years 19 days ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...