In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
Given an image region of pixels, second order statistics can be used to construct a descriptor for object representation. One example is the covariance matrix descriptor, which sh...
Xiaopeng Hong, Hong Chang, Shiguang Shan, Xilin Ch...
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...
Recent studies [13, 18] have shown that clearing schemes are efficient multi-modal optimization methods. They efficiently reduce genetic drift which is the direct reason for prema...