6926 search results - page 367 / 1386 » A More Effective CEFF |
175
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MTDT
1999
IEEE
15 years 11 months ago
1999
IEEE
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...
190
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ICS
1999
Tsinghua U.
15 years 11 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
180
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SIGCOMM
1998
ACM
15 years 11 months ago
1998
ACM
In this paper we develop a simple analytic characterization of the steady state throughput, as a function of loss rate and round trip time for a bulk transfer TCP flow, i.e., a ï...
204
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VVS
1996
IEEE
15 years 11 months ago
1996
IEEE
A critical issue in understanding high speed flows is the study of shock waves. This paper summarizes our research on techniques for the detection and visualization of shock waves...
151
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ISCA
1989
IEEE
15 years 11 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...