6926 search results - page 1110 / 1386 » A More Effective CEFF |
116
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...
190
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
182
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
146
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ICCD
2005
IEEE
16 years 3 months ago
2005
IEEE
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
168
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...