3394 search results - page 478 / 679 » A Modal Model of Memory |
177
click to vote
MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
203
click to vote
CF
2006
ACM
16 years 14 days ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
146
click to vote
SIGMETRICS
2005
ACM
16 years 1 days ago
2005
ACM
This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Us...
185
click to vote
MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
176
click to vote
MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...