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» A Modal Model of Memory
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PODC
2009
ACM
16 years 7 months ago
Partial synchrony based on set timeliness
d Abstract] Marcos K. Aguilera Microsoft Research Silicon Valley Mountain View, CA, USA Carole Delporte-Gallet Universit? Paris 7 Paris, France Hugues Fauconnier Universit? Paris ...
Marcos Kawazoe Aguilera, Carole Delporte-Gallet, H...
EUROPAR
1997
Springer
15 years 10 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
CASES
2001
ACM
15 years 10 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
16 years 7 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
16 years 2 days ago
In-system FPGA prototyping of an itanium microarchitecture
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Roland E. Wunderlich, James C. Hoe