1609 search results - page 235 / 322 » A Microeconomic Scheduler for Parallel Computers |
208
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
179
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HPCA
2007
IEEE
16 years 6 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
159
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IPPS
2007
IEEE
16 years 19 days ago
2007
IEEE
This paper describes the dynamic load-balancing and high performance communication provided in Jcluster, an efficient Java parallel environment. For the efficient loadbalancing,...
178
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IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
178
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...