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IPPS
2010
IEEE
15 years 4 months ago
Tile QR factorization with parallel panel processing for multicore architectures
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
Bilel Hadri, Hatem Ltaief, Emmanuel Agullo, Jack D...
IJNSEC
2008
106views more  IJNSEC 2008»
15 years 6 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
EUROPAR
2009
Springer
15 years 10 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
IEEEPACT
2003
IEEE
15 years 11 months ago
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, C...
GCC
2003
Springer
15 years 11 months ago
An Engineering Computation Oriented Visual Grid Framework
Grid computing technology is a focused field in high performance computing. This paper describes an engineering computation oriented visual grid framework VGrid, which is capable t...
Guiyi Wei, Yao Zheng, Jifa Zhang, Guanghua Song