1609 search results - page 104 / 322 » A Microeconomic Scheduler for Parallel Computers |
152
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ICPP
2003
IEEE
15 years 11 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
178
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HOTI
2002
IEEE
15 years 11 months ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
179
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IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
152
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CCGRID
2004
IEEE
15 years 10 months ago
2004
IEEE
1 Scheduling resources on Grids is a well-known problem. The extension of Grids to LambdaGrids requires scheduling of lambdas, i.e., end-to-end high-speed circuits. In this paper, ...
177
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CCGRID
2008
IEEE
15 years 8 months ago
2008
IEEE
In the current approaches to workflow scheduling, there is no cooperation between the distributed workflow brokers and as a result, the problem of conflicting schedules occur. To o...