360 search results - page 21 / 72 » A Method for the Verification of Haptic Algorithms |
190
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ICTAI
1997
IEEE
15 years 9 months ago
1997
IEEE
This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is abl...
185
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FORMATS
2007
Springer
15 years 9 months ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
183
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TOPLAS
2008
15 years 5 months ago
2008
act Interpretation C. BERNARDESCHI, N. DE FRANCESCO, G. LETTIERI, L. MARTINI, and P. MASCI Universit`a di Pisa Bytecode verification is a key point in the security chain of the Jav...
283
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FMCAD
1998
Springer
15 years 10 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
146
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ICCAD
2003
IEEE
16 years 2 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...