Sciweavers

2911 search results - page 349 / 583
» A Logic of Graph Constraints
Sort
View
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
15 years 12 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
VL
2002
IEEE
105views Visual Languages» more  VL 2002»
15 years 11 months ago
A Visual Framework for Modelling with Heterogeneous Notations
There is a range of modelling notations, both textual and diagrammatic, whose semantics are based on first-order predicate logic. This paper presents a visual framework for organ...
Jean Flower, John Howse, John Taylor, Stuart Kent
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
15 years 11 months ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
FLOPS
1999
Springer
15 years 11 months ago
Using Types as Approximations for Type Checking Prolog Programs
Abstract. Subtyping tends to undermine the effects of parametric polymorphism as far as the static detection of type errors is concerned. Starting with this observation we present...
Christoph Beierle, Gregor Meyer