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DATE
2006
IEEE
124views Hardware» more  DATE 2006»
16 years 20 days ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
16 years 6 days ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
ICLP
2004
Springer
15 years 12 months ago
On Programs with Linearly Ordered Multiple Preferences
The extended answer set semantics for logic programs allows for the defeat of rules to resolve contradictions. We propose a refinement of these semantics based on a preference rel...
Davy Van Nieuwenborgh, Stijn Heymans, Dirk Vermeir
CP
2003
Springer
15 years 11 months ago
Solving Max-SAT as Weighted CSP
For the last ten years, a significant amount of work in the constraint community has been devoted to the improvement of complete methods for solving soft constraints networks. We ...
Simon de Givry, Javier Larrosa, Pedro Meseguer, Th...
IJCAI
2003
15 years 8 months ago
Automatic Video Interpretation: A Novel Algorithm for Temporal Scenario Recognition
This paper presents a new scenario recognition algorithm for Video Interpretation. We represent a scenario model by specifying the characters involved in the scenario, the sub-sce...
Van-Thinh Vu, François Brémond, Moni...