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» A Logic of Abstract Argumentation
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SAC
2010
ACM
15 years 4 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 12 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
SEFM
2005
IEEE
16 years 4 days ago
Description Logics for Shape Analysis
Verification of programs requires reasoning about sets of program states. In case of programs manipulating pointers, program states are pointer graphs. Verification of such prog...
Lilia Georgieva, Patrick Maier
CAV
2004
Springer
99views Hardware» more  CAV 2004»
15 years 12 months ago
Range Allocation for Separation Logic
Abstract. Separation Logic consists of a Boolean combination of predicates of the form vi ≥ vj +c where c is a constant and vi, vj are variables of some ordered infinite type li...
Muralidhar Talupur, Nishant Sinha, Ofer Strichman,...
ENTCS
2002
125views more  ENTCS 2002»
15 years 6 months ago
Specification of Logic Programming Languages from Reusable Semantic Building Blocks
We present a Language Prototyping System that facilitates the modular development of interpreters from independent semantic buildks. The abstract syntax is modelled as the fixpoint...
José Emilio Labra Gayo, Juan Manuel Cueva L...