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DAC
2005
ACM
16 years 7 months ago
Structural search for RTL with predicate learning
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting...
DAC
2006
ACM
16 years 7 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
PERCOM
2006
ACM
16 years 6 months ago
Virtual Channel Management for Densely Deployed IEEE 802.15.4 LR-WPANs
The number of channels specified for IEEE 802.15.4 Low-Rate Wireless Personal Area Networks (LR-WPANs) is too few to operate many applications of WPANs in the same area. To overco...
Tae-Hyun Kim, Jae Yeol Ha, Sunghyun Choi, Wook Hyu...
FOCI
2007
IEEE
16 years 28 days ago
A New Reduction from 3SAT to n-Partite Graphs
— The Constraint Satisfaction Problem (CSP) is one of the most prominent problems in artificial intelligence, logic, theoretical computer science, engineering and many other are...
Daniel J. Hulme, Robin Hirsch, Bernard F. Buxton, ...
FMCAD
2007
Springer
16 years 22 days ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony