Sciweavers

3104 search results - page 468 / 621
» A High Performance Kernel-Less Operating System Architecture
Sort
View
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 8 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
16 years 18 hour ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
OSDI
2008
ACM
16 years 6 months ago
Towards Virtual Passthrough I/O on Commodity Devices
A commodity I/O device has no support for virtualization. A VMM can assign such a device to a single guest with direct, fast, but insecure access by the guest's native device...
Lei Xia, Jack Lange, Peter A. Dinda
OSDI
2004
ACM
16 years 6 months ago
FFPF: Fairly Fast Packet Filters
FFPF is a network monitoring framework designed for three things: speed (handling high link rates), scalability (ability to handle multiple applications) and flexibility. Multiple...
Herbert Bos, Willem de Bruijn, Mihai-Lucian Criste...
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
16 years 3 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...