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» A High Performance Kernel-Less Operating System Architecture
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AINA
2005
IEEE
16 years 7 days ago
3D-VOQ Switch Design and Evaluation
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Li...
IPPS
1997
IEEE
15 years 10 months ago
DPF: A Data Parallel Fortran Benchmark Suite
We present the Data Parallel Fortran (DPF) benchmark suite, a set of data parallel Fortran codes forevaluatingdata parallel compilers appropriatefor any target parallel architectu...
Y. Charlie Hu, S. Lennart Johnsson, Dimitris Kehag...
PC
2010
177views Management» more  PC 2010»
15 years 5 months ago
Parallel graph component labelling with GPUs and CUDA
Graph component labelling, which is a subset of the general graph colouring problem, is a computationally expensive operation that is of importance in many applications and simula...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne
CSE
2011
IEEE
14 years 6 months ago
Parallel Execution of AES-CTR Algorithm Using Extended Block Size
—Data encryption and decryption are common operations in a network based application programs with security. In order to keep pace with the input data rate in such applications, ...
Nhat-Phuong Tran, Myungho Lee, Sugwon Hong, Seung-...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 3 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen