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IOPADS
1996
100views more  IOPADS 1996»
15 years 8 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
HPCA
2009
IEEE
16 years 7 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 7 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
DILS
2007
Springer
16 years 23 days ago
Bioinformatics Service Reconciliation by Heterogeneous Schema Transformation
This paper focuses on the problem of bioinformatics service reconciliation in a generic and scalable manner so as to enhance interoperability in a highly evolving field. Using XML...
Lucas Zamboulis, Nigel J. Martin, Alexandra Poulov...
ASIACRYPT
2000
Springer
15 years 11 months ago
Key Improvements to XTR
Abstract. This paper describes improved methods for XTR key representation and parameter generation (cf. [4]). If the field characteristic is properly chosen, the size of the XTR ...
Arjen K. Lenstra, Eric R. Verheul