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DAC
2007
ACM
16 years 7 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 10 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
COMCOM
2006
138views more  COMCOM 2006»
15 years 6 months ago
Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
The needs for run-time data storage in modern wired and wireless network applications are increasing. Additionally, the nature of these applications is very dynamic, resulting in ...
Stylianos Mamagkakis, Christos Baloukas, David Ati...
ICASSP
2011
IEEE
14 years 10 months ago
Robust speech representation of voiced sounds based on synchrony determination with PLLs
We propose to include synchrony effects, known to exist in the auditory system, to represent voiced parts of the speech signal in a robust way. The system decomposes the input sig...
Patricia A. Pelle, Claudio Estienne, Horacio Franc...
IPPS
2005
IEEE
15 years 12 months ago
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems
The next generation of mobile systems with multimedia processing capabilities and wireless connectivity will be increasingly deployed in highly dynamic and distributed environment...
Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoung...