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SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
15 years 8 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
JSA
2006
86views more  JSA 2006»
15 years 6 months ago
The design and utility of the ML-RSIM system simulator
Execution-driven simulation has become the primary method for evaluating architectural techniques as it facilitates rapid design space exploration without the cost of building pro...
Lambert Schaelicke, Michael Parker
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
16 years 1 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
16 years 17 days ago
A parallel configuration model for reducing the run-time reconfiguration overhead
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
SP
2008
IEEE
100views Security Privacy» more  SP 2008»
16 years 27 days ago
Towards Practical Privacy for Genomic Computation
Many basic tasks in computational biology involve operations on individual DNA and protein sequences. These sequences, even when anonymized, are vulnerable to re-identification a...
Somesh Jha, Louis Kruger, Vitaly Shmatikov