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SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
16 years 2 days ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
15 years 11 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
ISCAS
2003
IEEE
128views Hardware» more  ISCAS 2003»
15 years 11 months ago
Robust digital image-in-image watermarking algorithm using the fast Hadamard transform
In this paper, a robust and efficient digital image watermarking algorithm using the fast Hadamard transform (FHT) is proposed for the copyright protection of digital images. This...
Anthony Tung Shuen Ho, Jun Shen, A. K. K. Chow, J....
DATE
2010
IEEE
109views Hardware» more  DATE 2010»
15 years 11 months ago
TIMBER: Time borrowing and error relaying for online timing error resilience
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram...
DATE
2010
IEEE
165views Hardware» more  DATE 2010»
15 years 11 months ago
Multicore soft error rate stabilization using adaptive dual modular redundancy
— The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can ...
Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson...