Sciweavers

1998 search results - page 213 / 400
» A Hardware Implementation of PRAM and Its Performance Evalua...
Sort
View
INTEGRATION
2007
98views more  INTEGRATION 2007»
15 years 6 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
PR
2010
135views more  PR 2010»
15 years 1 months ago
Revisiting priority queues for image analysis
Many algorithms in image analysis require a priority queue, a data structure that holds pointers to pixels in the image, and which allows efficiently finding the pixel in the queu...
Cris L. Luengo Hendriks
CASES
2000
ACM
15 years 10 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
MOBISYS
2005
ACM
16 years 6 months ago
An overlay MAC layer for 802.11 networks
The widespread availability of 802.11-based hardware has made it the premier choice of both researchers and practitioners for developing new wireless networks and applications. Ho...
Ananth Rao, Ion Stoica
PACS
2004
Springer
146views Hardware» more  PACS 2004»
15 years 12 months ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...