High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-specic integrated circuits (ASICs) and application-...
A growing interest in third generation wireless IP network and service technologies, push up the demand on IPv6 transition. Most of these services require mobility, multicast and m...
Yassine Hadjadj Aoul, Daniel Negru, Abdelhamid Naf...
—The paper presents a methodology that combines statistical learning with constraint optimization by locally optimizing Radio Resource Management (RRM) or system parameters of po...
Moazzam Islam Tiwana, Zwi Altman, Berna Sayra&cced...
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...