2370 search results - page 158 / 474 » A Framework for the Simulation Experimentation Process |
167
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CSCWD
2009
Springer
16 years 29 days ago
2009
Springer
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
201
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ECCV
2008
Springer
16 years 4 months ago
2008
Springer
Monte Carlo methods and their subsequent simulated annealing are able to minimize general energy functions. However, the slow convergence of simulated annealing compared with more ...
168
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CODES
2005
IEEE
16 years 1 days ago
2005
IEEE
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
202
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IJCNN
2000
IEEE
15 years 10 months ago
2000
IEEE
The field of human-computer interaction has been widely investigated in the last years, resulting in a variety of systems used in different application fields like virtual reality...
166
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VLSI
2007
Springer
16 years 15 days ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...