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» A Framework for Scheduler Synthesis
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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
16 years 3 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
CODES
2006
IEEE
16 years 6 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
EUROPAR
2005
Springer
15 years 11 months ago
Batch-Scheduling Dags for Internet-Based Computing
The process of scheduling computations for Internet-based computing presents challenges not encountered with more traditional platforms for parallel and distributed computing. The...
Grzegorz Malewicz, Arnold L. Rosenberg
IDEAS
2002
IEEE
113views Database» more  IDEAS 2002»
15 years 11 months ago
Scalable QoS-Aware Disk-Scheduling
A new quality of service (QoS) aware disk scheduling algorithm is presented. It is applicable in environments where data requests arrive with different QoS requirements such as re...
Walid G. Aref, Khaled El-Bassyouni, Ibrahim Kamel,...
CVPR
2009
IEEE
17 years 1 months ago
Human Motion Synthesis from 3D Video
Multiple view 3D video reconstruction of actor performance captures a level-of-detail for body and clothing movement which is time-consuming to produce using existing animation ...
Peng Huang (University of Surrey), Adrian Hilton (...