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» A Framework for Scheduler Synthesis
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ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 10 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
RTCSA
2009
IEEE
16 years 25 days ago
Towards Real Multi-criticality Scheduling
—Componentised systems, in particular those with fault confinement through address spaces, are currently emerging as a hot topic in embedded systems research. This paper extends...
Stefan M. Petters, Martin Lawitzky, Ryan Heffernan...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 6 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
IPPS
2009
IEEE
16 years 23 days ago
MGST: A framework for performance evaluation of Desktop Grids
Desktop Grids are rapidly gaining popularity as a costeffective computing platform for the execution of applications with extensive computing needs. As opposed to grids and cluste...
Majd Kokaly, Issam Al-Azzoni, Douglas G. Down