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» A Framework for Scheduler Synthesis
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ISER
2004
Springer
117views Robotics» more  ISER 2004»
15 years 11 months ago
Synthesis and Analysis of Non-Reactive Controllers for Multi-Robot Sequential Task Domains
In this paper we present a macroscopic model for the analysis of homogeneous task-directed multi-robot systems (MRS). The model is used to compute the probability that a given MRS ...
Chris Jones, Maja J. Mataric
DATE
2003
IEEE
152views Hardware» more  DATE 2003»
15 years 11 months ago
Synthesis of CMOS Analog Cells Using AMIGO
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud...
IJCSS
2007
133views more  IJCSS 2007»
15 years 6 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
IPPS
1997
IEEE
15 years 10 months ago
A BSP Approach to the Scheduling of Tightly-Nested Loops
This paper addresses the scheduling of uniformdependence loop nests within the framework of the bulksynchronous parallel (BSP) model. Two broad classes of tightly-nested loops are...
Radu Calinescu
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 3 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou