1420 search results - page 65 / 284 » A Framework for Scheduler Synthesis |
140
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
? The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic wa...
148
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ICCD
2002
IEEE
2002
IEEE
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
16 years 3 months ago
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
151
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DATE
2006
IEEE
16 years 5 days ago
2006
IEEE
The energy-aware design for electronic systems has been an important issue in hardware and/or software implementations, especially for embedded systems. This paper targets a synth...
167
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
186
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ISSS
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...