1420 search results - page 63 / 284 » A Framework for Scheduler Synthesis |
202
click to vote
SCOPES
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. Synthesis of digital signal processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. I...
190
click to vote
EUROMICRO
1999
IEEE
15 years 10 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
170
click to vote
GLVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
161
click to vote
CODES
2004
IEEE
15 years 9 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
164
click to vote
TVLSI
2008
15 years 6 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...