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» A Framework for Scheduler Synthesis
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CODES
1999
IEEE
15 years 10 months ago
Scheduling with optimized communication for time-triggered embedded systems
We present an approach to process scheduling for synthesis of safety-critical distributed embedded systems. Our system model captures both the flow of data and that of control. Th...
Paul Pop, Petru Eles, Zebo Peng
DATE
1997
IEEE
133views Hardware» more  DATE 1997»
15 years 10 months ago
Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors
This paper describes new algorithms for systemlevel software synthesis, namely the scheduling and allocation of a set of complex tasks running at multiple rates on a heterogeneous...
Yanbing Li, Wayne Wolf
RTAS
2005
IEEE
15 years 11 months ago
On Schedulability Bounds of Static Priority Schedulers
—Real-time systems need to use the schedulability test to determine whether or not admitted tasks can meet their deadlines. The utilization based schedulability test is the most ...
Jianjia Wu, Jyh-Charn Liu, Wei Zhao
ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
15 years 9 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
15 years 9 months ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella