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» A Framework for Scheduler Synthesis
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ICCAD
2002
IEEE
117views Hardware» more  ICCAD 2002»
16 years 3 months ago
An energy-conscious algorithm for memory port allocation
Multiport memories are extensively used in modern system designs because of the performance advantages they offer. The increased memory access throughput could lead to significan...
Preeti Ranjan Panda, Lakshmikantam Chitturi
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
16 years 13 days ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ICCD
2006
IEEE
134views Hardware» more  ICCD 2006»
16 years 12 days ago
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...
Krishnendu Chakrabarty
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
16 years 11 days ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ASPDAC
2008
ACM
88views Hardware» more  ASPDAC 2008»
15 years 8 months ago
REWIRED - Register Write Inhibition by Resource Dedication
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Pree...