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DAGSTUHL
2006
15 years 7 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver
BMCBI
2006
142views more  BMCBI 2006»
15 years 6 months ago
Improving the Performance of SVM-RFE to Select Genes in Microarray Data
Background: Recursive Feature Elimination is a common and well-studied method for reducing the number of attributes used for further analysis or development of prediction models. ...
Yuanyuan Ding, Dawn Wilkins
IJCAI
2007
15 years 7 months ago
Maximum Margin Coresets for Active and Noise Tolerant Learning
We study the problem of learning large margin halfspaces in various settings using coresets to show that coresets are a widely applicable tool for large margin learning. A large m...
Sariel Har-Peled, Dan Roth, Dav Zimak
FORMATS
2007
Springer
15 years 10 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson

Publication
189views
15 years 10 months ago
Direct Send Compositing for Parallel Sort-Last Rendering
In contrast to sort-first, sort-last parallel rendering has the distinct advantage that the task division for parallel geometry processing and rasterization is simple, and can eas...
Stefan Eilemann, Renato Pajarola