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INTERWORKING
2000
15 years 10 months ago
Design of a Multi-layer Bandwidth Broker Architecture
Internet is widely known for lacking any kind of mechanism for the provisioning of Quality of Service guarantees. The Internet community concentrates its efforts on the Bandwidth ...
George A. Politis, Petros Sampatakos, Iakovos S. V...
ESANN
2006
15 years 7 months ago
Gaussian and exponential architectures in small-world associative memories
The performance of sparsely-connected associative memory models built from a set of perceptrons is investigated using different patterns of connectivity. Architectures based on Gau...
Lee Calcraft, Rod Adams, Neil Davey
CODES
2000
IEEE
15 years 10 months ago
Compaan: deriving process networks from Matlab for embedded signal processing architectures
This paperpresents the Compaantool that automatically transforms a nestedloopprogram written in Matlab into a processnetwork specification. The processnetworkmodelof computation...
Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
15 years 11 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
PREMI
2005
Springer
15 years 12 months ago
Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the...
Milene Barbosa Carvalho, Alexandre Marques Amaral,...