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HPCA
2008
IEEE
16 years 7 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
HICSS
2007
IEEE
122views Biometrics» more  HICSS 2007»
16 years 1 months ago
Enterprise Information Architecture (EIA): Assessment of Current Practices in Malaysian Organizations
In this paper we described the findings based on a research study on current Enterprise Information Architecture (EIA) practices in Malaysian organizations. Ten organizations from...
Rafidah Abd. Razak, Zulkhairi Md. Dahalin, Rohaya ...
IJCNN
2007
IEEE
16 years 1 months ago
Robotic Architecture Inspired on Behavior Analysis
Learning by human tutelage means that a human being guides the attention of a robot or agent in order to teach it a given concept. This kind of learning is very important to devel...
Claudio A. Policastro, Roseli A. F. Romero, Giovan...
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ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
16 years 26 days ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 11 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey