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IPPS
2005
IEEE
16 years 4 days ago
Virtual Gateways in the DECOS Integrated Architecture
— The DECOS architecture aims at combining the advantages of federated and integrated systems. The DECOS architecture divides the overall system into a set of nearly-independent ...
Roman Obermaisser, Philipp Peti, Hermann Kopetz
SBRN
1998
IEEE
15 years 10 months ago
A Neural Architecture for the Identification of Number Sequences
This paper describes an architecture based on spatiotemporal networks that identifies sequences of numbers. This architecture incorporates an input layer that transforms (by means...
Juan Moreno García, Gabriel Sebastiá...
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
16 years 28 days ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
ICCAD
2005
IEEE
95views Hardware» more  ICCAD 2005»
16 years 3 months ago
Application-specific network-on-chip architecture customization via long-range link insertion
Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either complete...
Ümit Y. Ogras, Radu Marculescu
IPPS
2006
IEEE
16 years 17 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...