6188 search results - page 1017 / 1238 » A DoS-limiting network architecture |
166
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
155
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
164
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
170
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
176
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WWW
2008
ACM
16 years 7 months ago
2008
ACM
Supporting fast access to large RDF stores has been one of key challenges for enabling use of the Semantic Web in real-life applications, more so in sensor-based systems where lar...