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ICS
2000
Tsinghua U.
15 years 10 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
IJCAI
1989
15 years 7 months ago
Real-Time AI Systems: A Definition and An Architecture
Speed alone is insufficient for real-time performance. We define real-time performance in terms of speed, responsiveness, timeliness, and graceful adaptation. We claim that all fo...
Rajendra T. Dodhiawala, N. S. Sridharan, Peter Rau...
EUROPAR
2010
Springer
15 years 7 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
HPCA
2006
IEEE
16 years 6 months ago
Dynamic power-performance adaptation of parallel computation on chip multiprocessors
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
Jian Li, José F. Martínez
GCC
2007
Springer
15 years 8 months ago
Toward a Logical Architecture for Situation Dependent Information Services with Surrounding Awareness
In recent years, the rapid growth of m-commerce is being driven by various emerging mobile applications and services. Among them, mobile information service is considered to be on...
Xiaojun Ding, Junichi Iijima