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HPCA
1998
IEEE
15 years 11 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
ICS
1995
Tsinghua U.
15 years 10 months ago
Gated SSA-based Demand-Driven Symbolic Analysis for Parallelizing Compilers
In this paper, we present a GSA-based technique that performs more e cient and more precise symbolic analysis of predicated assignments, recurrences and index arrays. The e ciency...
Peng Tu, David A. Padua
IEEEPACT
2009
IEEE
16 years 1 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
PADS
2006
ACM
16 years 16 days ago
Aurora: An Approach to High Throughput Parallel Simulation
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
Alfred Park, Richard M. Fujimoto
ICPP
2003
IEEE
15 years 12 months ago
FastLSA: A Fast, Linear-Space, Parallel and Sequential Algorithm for Sequence Alignment
Pairwise sequence alignment is a fundamental operation for homology search in bioinformatics. For two DNA or protein sequences of length ¢ and £ , full-matrix (FM), dynamic prog...
Adrian Driga, Paul Lu, Jonathan Schaeffer, Duane S...