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DATE
1999
IEEE
92views Hardware» more  DATE 1999»
15 years 11 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
SPRINGSIM
2007
15 years 8 months ago
CD++Builder: an eclipse-based IDE for DEVS modeling
Modeling and simulation tools have been used for helping in the early stages of hardware/software systems design. The DEVS formalism is a technique that enables hierarchical descr...
Chiril Chidisiuc, Gabriel A. Wainer
SIGMOD
2009
ACM
175views Database» more  SIGMOD 2009»
16 years 7 months ago
QoX-driven ETL design: reducing the cost of ETL consulting engagements
As business intelligence becomes increasingly essential for organizations and as it evolves from strategic to operational, the complexity of Extract-Transform-Load (ETL) processes...
Alkis Simitsis, Kevin Wilkinson, Malú Caste...
IJCAI
2007
15 years 8 months ago
Automated Benchmark Model Generators for Model-Based Diagnostic Inference
This article proposes a Diagnosis Interchange Format (DIF), an XML-based interchange format for Model-Based Diagnosis (MBD). Its main purposes are to allow sharing of diagnostic m...
Gregory M. Provan, Jun Wang
DAC
2008
ACM
16 years 7 months ago
Daedalus: toward composable multimedia MP-SoC design
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
Hristo Nikolov, Mark Thompson, Todor Stefanov, And...