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CSREAESA
2006
15 years 8 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
PROCEDIA
2010
138views more  PROCEDIA 2010»
15 years 1 months ago
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...
LCN
2008
IEEE
16 years 1 months ago
DiCAP: Distributed Packet Capturing architecture for high-speed network links
— IP traffic measurements form the basis of several network management tasks, such as accounting, planning, intrusion detection, and charging. High-speed network links challenge ...
Cristian Morariu, Burkhard Stiller
ESWS
2005
Springer
16 years 5 days ago
DRAGO: Distributed Reasoning Architecture for the Semantic Web
The paper addresses the problem of reasoning with multiple ontologies interrelated with semantic mappings. This problem is becoming more and more relevant due to the necessity of b...
Luciano Serafini, Andrei Tamilin
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
16 years 21 days ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...