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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 3 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
VMCAI
2009
Springer
16 years 1 months ago
Synthesizing Switching Logic Using Constraint Solving
A new approach based on constraint solving techniques was recently proposed for verification of hybrid systems. This approach works by searching for inductive invariants of a give...
Ankur Taly, Sumit Gulwani, Ashish Tiwari
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
16 years 21 days ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
IJCNN
2006
IEEE
16 years 20 days ago
An Interval Type-II Robust Fuzzy Logic Controller for a Static Compensator in a Multimachine Power System
—This paper presents a novel fuzzy logic based controller for a Static Compensator (STATCOM) connected to a power system. Type-II fuzzy systems are selected that enable the contr...
Salman Mohagheghi, Ganesh K. Venayagamoorthy, Rona...
TIME
1999
IEEE
15 years 11 months ago
TALplanner: An Empirical Investigation of a Temporal Logic-Based Forward Chaining Planner
We present a new forward chaining planner, TALplanner, based on ideas developed by Bacchus [5] and Kabanza [11], where domain-dependent search control knowledge represented as tem...
Patrick Doherty, Jonas Kvarnström