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HPCA
1998
IEEE
15 years 10 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
15 years 10 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
ASPLOS
2010
ACM
16 years 17 days ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 10 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
MSWIM
2005
ACM
15 years 11 months ago
Cellular universal IP: a low delay mobility scheme based on universal IP addressing
The concept of care-of-address (CoA) is a major cause of excessive handoff delay in Mobile IPv6 for real time multimedia traffic. Many schemes eliminate the use of CoA at the micr...
Patrick P. Lam, Soung C. Liew, Jack Y. B. Lee