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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
HRI
2009
ACM
16 years 1 months ago
Field trial for simultaneous teleoperation of mobile social robots
Simultaneous teleoperation of mobile, social robots presents unique challenges, combining the real-time demands of conversation with the prioritized scheduling of navigational tas...
Dylan F. Glas, Takayuki Kanda, Hiroshi Ishiguro, N...
SIGMETRICS
2009
ACM
149views Hardware» more  SIGMETRICS 2009»
16 years 1 months ago
On the treeness of internet latency and bandwidth
Existing empirical studies of Internet structure and path properties indicate that the Internet is tree-like. This work quantifies the degree to which at least two important Inte...
Venugopalan Ramasubramanian, Dahlia Malkhi, Fabian...
ECCV
2004
Springer
16 years 8 months ago
Line Geometry for 3D Shape Understanding and Reconstruction
We understand and reconstruct special surfaces from 3D data with line geometry methods. Based on estimated surface normals we use approximation techniques in line space to recogniz...
Helmut Pottmann, Michael Hofer, Boris Odehnal, Joh...
DAC
2002
ACM
16 years 7 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...