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GLVLSI
2009
IEEE
131views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Octilinear redistributive routing in bump arrays
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections. Traditional RDL routing designs are mostly performed man...
Renshen Wang, Chung-Kuan Cheng
TCAD
2008
103views more  TCAD 2008»
15 years 6 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
TALG
2010
86views more  TALG 2010»
15 years 5 months ago
Approximating corridors and tours via restriction and relaxation techniques
Given a rectangular boundary partitioned into rectangles, the Minimum-Length Corridor (MLC-R) problem consists of finding a corridor of least total length. A corridor is a set of ...
Arturo Gonzalez-Gutierrez, Teofilo F. Gonzalez
CODES
2011
IEEE
14 years 6 months ago
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
DAC
2003
ACM
16 years 2 days ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich