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DAC
2009
ACM
16 years 7 months ago
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
16 years 1 months ago
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits...
Almitra Pradhan, Ranga Vemuri
GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
16 years 10 days ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
ICNP
2000
IEEE
15 years 11 months ago
A Topology-Independent Fair Queueing Model in Ad Hoc Wireless Networks
Fair queueing of rate and delay-sensitive packet flows in a shared-medium, multihop wireless network remains largely unaddressed because of the unique design issues such as locat...
Haiyun Luo, Songwu Lu
DAC
2005
ACM
15 years 8 months ago
TCAM enabled on-chip logic minimization
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory e...
Seraj Ahmad, Rabi N. Mahapatra