We propose a probabilistic network model, called asynchronous bounded expected delay (ABE), which requires a known bound on the expected message delay. In ABE networks all asynchr...
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...