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IPL
2011
91views more  IPL 2011»
14 years 10 months ago
Fast leader election in anonymous rings with bounded expected delay
We propose a probabilistic network model, called asynchronous bounded expected delay (ABE), which requires a known bound on the expected message delay. In ABE networks all asynchr...
Rena Bakhshi, Jörg Endrullis, Wan Fokkink, Ju...
DAC
2000
ACM
16 years 7 months ago
Unifying behavioral synthesis and physical design
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
William E. Dougherty, Donald E. Thomas
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 3 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
16 years 7 days ago
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
DAC
2000
ACM
16 years 7 months ago
The design and use of simplepower: a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...