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126
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DATE
2006
IEEE
16 years 14 days ago
2006
IEEE
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
175
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DAC
2003
ACM
15 years 11 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
143
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ARITH
1999
IEEE
15 years 10 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
135
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NSDI
2008
15 years 8 months ago
2008
The systems and networking community treasures "simple" system designs, but our evaluation of system simplicity often relies more on intuition and qualitative discussion...
161
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DAC
2010
ACM
15 years 8 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...