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ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
15 years 12 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
15 years 10 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
IWCMC
2006
ACM
16 years 11 days ago
Low complexity design of space-time convolutional codes with high spectral efficiencies
Space time convolutional codes (STCCs) are an effective way to combine transmit diversity with coding. The computational complexity of designing STCCs generally increases exponent...
Kyungmin Kim, Hamid R. Sadjadpour, Rick S. Blum, Y...
PODC
2009
ACM
16 years 7 months ago
Bounding the locality of distributed routing algorithms
d Abstract] Prosenjit Bose School of Computer Science Carleton University Ottawa, Canada jit@scs.carleton.ca Paz Carmi Dept. of Computer Science Ben-Gurion Univ. of the Negev Beer-...
Prosenjit Bose, Paz Carmi, Stephane Durocher
DAC
2008
ACM
16 years 7 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta