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» A Compiler for the Smart Space
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SAC
2004
ACM
15 years 11 months ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
15 years 11 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 11 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
SAC
2002
ACM
15 years 5 months ago
Automatic code generation for executing tiled nested loops onto parallel architectures
This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widel...
Georgios I. Goumas, Maria Athanasaki, Nectarios Ko...
USS
2010
15 years 4 months ago
Cling: A Memory Allocator to Mitigate Dangling Pointers
Use-after-free vulnerabilities exploiting so-called dangling pointers to deallocated objects are just as dangerous as buffer overflows: they may enable arbitrary code execution. U...
Periklis Akritidis