Sciweavers

495 search results - page 55 / 99
» A Compiler for the Smart Space
Sort
View
ICS
2005
Tsinghua U.
15 years 11 months ago
Think globally, search locally
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
Kamen Yotov, Keshav Pingali, Paul Stodghill
CASES
2007
ACM
15 years 10 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
SPAA
2010
ACM
15 years 6 months ago
Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures
We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling. Compared to previous multi-core stream scheduling algorithms, team schedu...
JongSoo Park, William J. Dally
ISCAS
2006
IEEE
160views Hardware» more  ISCAS 2006»
16 years 9 days ago
Address-event image sensor network
We describe a sensor network based on smart requirements of the network. This will provide a new approach imager sensors able to extract events of interest from a scene. for compos...
Eugenio Culurciello, Andreas Savvides
TACAS
2001
Springer
160views Algorithms» more  TACAS 2001»
15 years 10 months ago
Hardware/Software Co-Design Using Functional Languages
In previous work we have developed and prototyped a silicon compiler which translates a functional language (SAFL) into hardware. Here we present a SAFL-level program transformati...
Alan Mycroft, Richard Sharp