—The advent of practical rateless codes enables implementation of highly efficient packet-level forward error correction (FEC) strategies for reliable data broadcasting in loss-...
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
In this paper we generalize the Continuous Adversarial Queuing Theory (CAQT) model [5] by considering the possibility that the router clocks in the network are not synchronized. W...
Algorithms for determining quality/cost/price tradeoffs in saturated markets are consid-3 ered. A product is modeled by d real-valued qualities whose sum determines the unit cost ...
Joachim Gudmundsson, Pat Morin, Michiel H. M. Smid
People travel between places of residence and work destinations via transportation net-
works. The relation between selection of home and work locations has been heavily
debated ...